The design and verification of integrated circuit designs is becoming increasingly complex. To this end, computer aided design is an integral part of the design cycle of integrated circuits, and the role of accurate and efficient computer aided design is becoming increasingly predominant. Particularly challenging are high frequency integrated circuits incorporating both analog and digital components. The interface between the analog and digital portions of the circuit imposes special challenges since traditional digital simulation techniques and traditional analog simulation techniques are frequently both inadequate to accurately capture circuit behavior in a way that is efficient to simulate.
Certain types of circuits are particularly problematic in this regard, such as those performing the functions of a phase locked loop (PLL) or a serializer/deserializer (SERDES). These circuits present difficulties because they have high frequency signals, but change slowly in response to other inputs. A harmonic balance analysis, which is commonly used to analyze analog circuits, can be prohibitively expensive because the number of harmonics necessary to capture both the high frequency and low frequency behavior would be very large. Alternatively, an accurate time-domain simulation, commonly used in digital circuit analysis, can also be prohibitively expensive. This is because the steps have to be small in order to capture the high frequency components and the number of steps have to be large to capture the overall circuit behavior and the processing of the information-carrying signal. Furthermore, since the analog nature of the signals need to be captured, the amount of computation that must be performed at each time step is significant.
As a result of these shortcomings, circuits bridging analog and digital components are often simulated in a way that lacks accuracy. In particular, the output stages of circuit blocks are approximated based on simplistic assumptions that do not reflect the actual circuit behavior. This can cause integrated circuits to be built with unexpected behavior, leading to time-consuming and expensive re-design. Thus, what is needed is a method of modeling circuit blocks accurately so that efficient time domain simulations can be performed without sacrificing the accuracy of the results.